The present invention relates to a microprocessor which is capable of protecting confidential information that it holds from illegitimate access attempts made through an external bus interface.
Laid-open patent specification No. 2001-306400 (corresponding U.S. publication of unexamined application No. 2002/0018384A1) discloses a scheme by which a security circuit that is situated between a memory and a memory interface control circuit monitors memory access to ensure that it conforms to a prescribed protocol. The security circuit uses a combination of a key address that is assigned to it and its associated protocol to expand the area(s) that can be accessed within the memory space or to determine the area(s) that can be accessed by anticipated access requests and protect the remainder of the memory space from being accessed for data transfer. Under this scheme, when an attempt is made to access an area which is still protected, the validity of the read data is not guaranteed.
In the above-described system, only the external memory space was subject to protection: the processor's internal memory was not. However, expanding this scheme to cover the processor's entire internal memory space would significantly increase the amount of redundant logic circuits, making the processor bulky.
The scheme disclosed in the above-referenced laid-open patent specification lacks flexibility and expandability, since it uses hardware logic to determine whether memory protection applies or not, according to the sequence in which memory addresses are accessed.
Still another problem with such a scheme is that, in a processor not equipped with a protection mechanism, it is easy to read or alter the contents of a register or a local memory inside the processor through an external bus. As a result, confidential data, such as cryptographic keys, can be stolen, or a newly developed piece of software can be copied.